The present invention relates to a method of etching polysilicon layer used in a semiconductor integrated circuit (IC) and others.
The higher integration and performance have been progressed in the ICs recently. One of these technology trends is to develop a Metal-Oxide-Silicon (MOS) transistor of which components including wiring are designed as small as in a submicron unit. Under a design rule of such a MOS transistor employing a submicron unit, a thickness of silicon dioxide film, which comprises a gate insulating layer, is as thin as not more than 20 nm. Accordingly, in an etching process of the polysilicon layer, it is crucial to obtain a selectivity between polysilicon layer and silicon dioxide layer which is an underlayer of polysilicon layer. (Selectivity: an etching speed ratio of polysilicon layer vs. silicon dioxide layer)
FIG. 7 illustrates a conventional etching method of the polysilicon layer. A sample to be etched comprises as follows: A silicon dioxide layer 2 is formed on a silicon substrate 1, and a polysilicon layer 3 is formed thereon, further a resist layer 4, a mask, is formed on the polysilicon layer 3. For etching the polysilicon layer 3, chlorine system gas, bromine system gas or mixed gas of them is used.
When the silicon dioxide layer 2 is exposed in the polysilicon layer 2 during the etching process, the silicon dioxide layer 2 starts being etched by carbon emitted from the resist layer 4 following the reaction formula below: EQU --Si--O-+C+Br (or Cl).fwdarw.C--O+Si--Br (or Si--Cl)
Through the above conventional method, since carbon is emitted from the resist layer 4, it is very difficult to heighten the selectivity. In particular as shown in FIG. 8, when the silicon dioxide layer 2 becomes thinner, the etching progresses as far as into the silicon substrate 1. Therefore, it has been difficult to obtain high reliability in IC circuitry, and it still remains as an issue.